Advances in semiconductor processes require the development of higher integration density processes, which continue to become more difficult to achieve. Over the past half century, the growth rate of semiconductor device performance has followed the famous Moore's Law. Advanced semiconductor processes have developed from planar structures to 3D structures, transistor areas have been shrinking, and the number of transistors that can be accommodated in integrated circuits has doubled in about 18 months. According to the MKS instrument manual information, we can see that the 3D NAND architecture stacks memory cells to reduce the overall footprint; FinFET transistors are manufactured using a 3D method to reduce tunneling effects. With the increase in the integration of semiconductor devices, the industry needs to use more complex manufacturing processes, which puts forward higher requirements for materials and equipment.

The number of semiconductor manufacturing processes at nodes of 4nm and below has increased to nearly 1,000, and the yield of each process needs to exceed 99.99 to ensure the overall yield reaches 95%. According to Yole data (quoted from "China Integrated Circuit Testing and Testing Industry Technology Innovation Roadmap" (Integrated Circuit Testing Instrument and Equipment Industry Technology Innovation Alliance)), the number of fatal defects generated in the process will increase by 50% for each generation of process nodes, and the yield of each process must be maintained at a very high level to ensure the final yield. According to the announcement of China Science and Technology, the process steps of 28nm process node have hundreds of processes. Due to the use of multi-layer overlay technology, the process steps of 14nm and below nodes have increased to nearly 1,000 processes. When there are more than 500 processes, the final yield can exceed 95% only if the yield of each process exceeds 99.99. When the yield of a single process drops to 99.98, the final total yield will drop to about 90%. Therefore, the challenges to the process window in the manufacturing process require almost "zero defects".

The cost of advanced process chips is rapidly increasing, and IBS data show that the investment in 3nm process wafer equipment will reach 21.5 billion yuan per 50000 chips. Driven by Moore's Law, the significant increase in the integration of components requires the continuous reduction of the line width of integrated circuits, resulting in more complex production technology and manufacturing processes, and an exponential upward trend in manufacturing costs. According to IBS statistics (quoted from SMIC's prospectus), as technology nodes continue to shrink, equipment investment in integrated circuit manufacturing is on a significant upward trend. Take the 5nm technology node as an example, its investment cost is as high as $15.6 billion, which is more than twice that of 14nm and about four times that of 28nm. Therefore, the chip factory flow chip cost has also increased significantly, according to The Information Network data, 12nm process flow chip cost of about $300-5 million, 5nm process flow chip cost of $4000-50 million, the cost of using 2nm process flow chip as high as $0.1 billion.